Publication
Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters
Kemal Çağlar Coşkun; Muhammad Hassan; Rolf Drechsler
In: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2022), April 6-8, Prague, Czech Republic, 2022.
Abstract
Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level methodologies, which provide speed benefits in comparison to SPICE simulations and allow interoperability with digital tools at the system-level. However, a key barrier to the expansion of system-level tools for analog circuits is the lack of confidence in system-level models implemented in SystemC AMS. To overcome this, functional equivalence of system-level models to respective SPICE-level models needs to be demonstrated. In this paper, we develop a novel, graph based methodology to formally check equivalence between system-level and SPICE-level representations of linear analog filter circuits, such as Low-Pass Filters (LPF). To do this, we propose an intermediate representation in the form of a Signal-flow Graph (SFG), which acts as a mapping function from the SPICE-level to the system-level. We create the intermediate representation with linear graph modeling from the SPICE-level model and use graph manipulation to transform the intermediate representation to the equivalent system-level model. We demonstrate the applicability of the proposed methodology by successfully applying it to two example filters.