Publications

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Sören Tempel; Vladimir Herdt; Rolf Drechsler
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing
In: 58th Design Automation Conference (DAC). Design Automation Conference (DAC-2021), December 5-9, San Francisco, CA, USA, 2021.
Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
In: 24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). ITG/GMM/GI-Workshop …
Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler
MircoRV32: An Open Source RISC-V Cross-Level Platform for Education and Research
In: 2021 IEEE Workshop on Design Automation for CPS and IoT (DESTION 2021). Design Automation for CPS and IoT (DESTION-2021), located at IEEE/ACM …
Pascal Pieper; Ralf Wimmer; Gerhard Angst; Rolf Drechsler
Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level
In: 31st ACM Great Lakes Symposium on VLSI (GLSVLSI). ACM Great Lakes Symposium on VLSI (GLSVLSI-2021), June 22-25, 2021.
Mehran Goli; Alireza Mahzoon; Rolf Drechsler
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
In: Euromicro Conference on Digital System Design (DSD). Euromicro Conference on Digital System Design (DSD-2021), September 1-3, Palermo/Virtual, …
Sören Tempel; Vladimir Herdt; Rolf Drechsler
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes
In: Forum on Specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL-2021), September 8-10, Antibes/Hybrid, France, …
Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler
RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems
In: Forum on Specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL-2021), September 8-10, Antibes/Hybrid, France, …
Frank Riese; Vladimir Herdt; Daniel Große; Rolf Drechsler
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level
In: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IFIP/IEEE International Conference on Very Large Scale Integration …
Mehran Goli; Rolf Drechsler
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes
In: Forum on Specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL), September 8-10, Antibes/Hybrid, France, 2021.
Mehran Goli; Rolf Drechsler
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs
In: 40th International Conference on Computer Aided Design (ICCAD). IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2021), November …