Robotics Innovation Center

Publications

Page 4 of 59.

Sallar Ahmadi-Pour; Muhammad Hassan; Rolf Drechsler
Cross-Level Verification of Hardware Peripherals
In: RISC-V Summit Europe. RISC-V Summit Europe, June 24-28, München, Germany, 2024.
Christina Plump; Daniel C. Hoinkiss; Jörn Huber; Bernhard J. Berger; Matthias Günther; Christoph Lüth; Rolf Drechsler
Finding the perfect MRI sequence for your patient --- Towards an optimisation workflow for MRI-sequences
In: The IEEE World Congress on Computational Intelligence. IEEE World Congress on Computational Intelligence (WCCI-2024), June 30 - July 5, Yokohama, …
Khushboo Qayyum; Muhammad Hassan; Sallar Ahmadi-Pour; Chandan Jha; Rolf Drechsler
From Bugs to Fixes: HDL Bug Identification and Patching using LLMs and RAG
In: Proceedings of the First IEEE International Workshop on LLM-Aided Design (LAD'24). IEEE International Workshop on LLM-Aided Design (LAD-24), June …
Kamalika Datta; Rolf Drechsler
Special issue on in-memory computing: Circuits, system, architecture and verification
In: Memories - Materials, Devices, Circuits and Systems, Vol. 5, Pages 1-3, Science Direct, 10/2023.
Rune Krauss; Mehran Goli; Rolf Drechsler
EDDY: A Multi-Core BDD Package With Dynamic Memory Management and Reduced Fragmentation
In: Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASP-DAC). Asia and South Pacific Design Automation Conference …
Arighna Deb; Kamalika Datta; Muhammad Hassan; Saeideh Shirinzadeh; Rolf Drechsler
Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars
In: Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASP-DAC). Asia and South Pacific Design Automation Conference …
Jan Kleinekathöfer; Alireza Mahzoon; Rolf Drechsler
Polynomial Formal Verification of Floating Point Adders
In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.
Niklas Bruns; Vladimir Herdt; Rolf Drechsler
Processor Verification using Symbolic Execution: A RISC-V Case-Study
In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.
Kemal Çağlar Coşkun; Muhammad Hassan; Rolf Drechsler
Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits
In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.
Sajjad Parvin; Mehran Goli; Frank Sill Torres; Rolf Drechsler
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing
In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

Links

Robotics Innovation Center

Cross-Level Verification of Hardware Peripherals

Finding the perfect MRI sequence for your patient --- Towards an optimisation workflow for MRI-sequences

From Bugs to Fixes: HDL Bug Identification and Patching using LLMs and RAG

Special issue on in-memory computing: Circuits, system, architecture and verification

EDDY: A Multi-Core BDD Package With Dynamic Memory Management and Reduced Fragmentation

Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars

Polynomial Formal Verification of Floating Point Adders

Processor Verification using Symbolic Execution: A RISC-V Case-Study

Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits

FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing

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Contact

Main site in Bremen