Publications

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Weiyan Zhang; Muhammad Hassan; Rolf Drechsler
Towards ML-based Performance Estimation of Embedded Software: A RISC-V Case Study
In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). ITG/GMM/GI-Workshop "Methoden und …
Tim Henkes; Steffen Reith; Marc Stöttinger; Norbert Herfurth; Goran Panic; Julian Wälde; Fabian Buschkowski; Pascal Sasdrich; Christoph Lüth; Milan Funck; Tuba Kiyan; Arnd Weber; Detlef Boeck; René Rathfelder; Torsten Grawunder
Evaluating an open-source hardware approach from HDL to GDS for a security chip design — a review of the final stage of project HEP
In: Design, Automation and Test in Europe. Design, Automation & Test in Europe (DATE-2024), March 25-27, Valencia, Spain, 2024.
Jan Zielasko; Rune Krauss; Marcel Merten; Rolf Drechsler
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences
In: 27th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and …
Sören Tempel; Tobias Brandt; Christoph Lüth; Rolf Drechsler
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models
In: Forum on specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL-2023), September 13-15, Turin, Italy, 2023.
Weiyan Zhang; Mehran Goli; Muhammad Hassan; Rolf Drechsler
Efficient ML-Based Performance Estimation Approach across Different Microarchitectures for RISC-V Processors
In: Euromicro Conference Series on Digital System Design (DSD). Euromicro Conference on Digital System Design (DSD-2023), September 6-8, Durres, …
Milan Funck; Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification
In: FDL. Forum on Specification & Design Languages (FDL-2023), September 12-15, Turin, Italy, IEEE, 2023.
Jan Zielasko; Rolf Drechsler
Virtual Prototype driven Application Specific Hardware Optimization
In: Forum on Specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL-2023), September 13-15, Turin, Italy, 2023.

Towards ML-based Performance Estimation of Embedded Software: A RISC-V Case Study

Evaluating an open-source hardware approach from HDL to GDS for a security chip design — a review of the final stage of project HEP

Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models

Efficient ML-Based Performance Estimation Approach across Different Microarchitectures for RISC-V Processors

Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification

Virtual Prototype driven Application Specific Hardware Optimization