Publication
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences
Jan Zielasko; Rune Krauss; Marcel Merten; Rolf Drechsler
In: 27th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2024), April 3-5, Kielce, Poland, 2024.
Abstract
Tailoring hardware to an application significantly
enhances its performance compared to using a general-purpose
processor. While hardware optimization is essential to meet the
user requirements for resource-constrained embedded systems, it
generally entails considerable costs and a high level of effort. In
recent work virtual prototypes have been shown to be an effective
analysis tool for guiding this process. In best-case scenarios, it is
possible to identify a single recurring instruction sequence that
covers approximately 55 % of all executed instructions and is
thus suitable for optimization by a Hardware Accelerator (HA).
However, challenges arise for applications where each identified
sequence only covers a small fraction of the total execution.
In order to achieve comparable coverage, several HAs can be
designed, but this also multiplies the hardware costs. To address
these issues, this work proposes an approach to extend and
merge identified sequences allowing the design of a single HA
for the merged sequence. Experiments show that this approach
significantly increases the coverage achievable with a single HA
while the resulting performance loss is negligible compared to
building multiple HAs.