Assistierender Roboterarm am Krankenbett (links), Hightech Chip (mittig), Fussball spielende Nao Roboter (rechts)

Cyber-Physical Systems

Publications

Page 2 of 106.

Weiyan Zhang; Muhammad Hassan; Rolf Drechsler
Towards ML-based Performance Estimation of Embedded Software: A RISC-V Case Study
In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). ITG/GMM/GI-Workshop "Methoden und …
Payam Habiby; Fatemeh Shirinzadeh; Rolf Drechsler
An Evolutionary Approach to Reconfigurable Scan Network Design
In: 36. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ). GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von …
Tim Henkes; Steffen Reith; Marc Stöttinger; Norbert Herfurth; Goran Panic; Julian Wälde; Fabian Buschkowski; Pascal Sasdrich; Christoph Lüth; Milan Funck; Tuba Kiyan; Arnd Weber; Detlef Boeck; René Rathfelder; Torsten Grawunder
Evaluating an open-source hardware approach from HDL to GDS for a security chip design — a review of the final stage of project HEP
In: Design, Automation and Test in Europe. Design, Automation & Test in Europe (DATE-2024), March 25-27, Valencia, Spain, 2024.
Muhammad Hassan; Sallar Ahmadi-Pour; Khushboo Qayyum; Chandan Kumar Jha; Rolf Drechsler
LLM-guided Formal Verification Coupled with Mutation Testing
In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2024), March 25-27, Valencia, Spain, 2024.
Sajjad Parvin; Chandan Jha; Frank Sill Torres; Rolf Drechsler
Hidden Cost of Circuit Design with RFETs
In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2024), March 25-27, Valencia, Spain, 2024.
Khushboo Qayyum; Sallar Ahmadi-Pour; Muhammad Hassan; Chandan Kumar Jha; Rolf Drechsler
LLM-Assisted High Quality Invariants Generation for Formal Verification
In: Design, Automation & Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2024), March 25-27, Valencia, Spain, 2024.
Jan Zielasko; Rune Krauss; Marcel Merten; Rolf Drechsler
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences
In: 27th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and …
Caroline Dominik; Rolf Drechsler
Polynomial Formal Verification of Sequential Circuits
In: Design, Automation & Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2024), March 25-27, Valencia, Spain, 2024.
Mohamed Nadeem; Chandan Jha; Rolf Drechsler
Polynomial Formal Verification of Approximate Adders with Constant Cutwidth
In: 29th IEEE European Test Symposium 2024. IEEE European Test Symposium (ETS-2024), May 20-24, The Hague, Netherlands, 2024.
Payam Habiby; Fatemeh Shirinzadeh; Sebastian Huhn; Rolf Drechsler
A Multi-Objective Evolutionary Approach for Test Network Design
In: IEEE 29th European Test Symposium. IEEE European Test Symposium (ETS-2024), May 20-24, Den Haag, Netherlands, 2024.