Publication
Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains
Payam Habiby; Sebastian Huhn; Rolf Drechsler
In: 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 2020. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT-2020), ISBN 978-1-7281-9457-8, IEEE, 2020.
Abstract
New test access methodologies are required to cope
with the ever-increasing complexity of latest system-on-a-chip
designs. The IEEE 1687 standard defines an access methodology
to embedded instruments through a reconfigurable scan
infrastructure. This technique allows implementing even large
networks while keeping the individual access time low since only
relevant parts of the scan chain are included in the scan path.
However, the reconfiguration introduces a timing overhead, which
can be mitigated by accessing instruments concurrently. The
concurrent activation of instruments forms a critical aspect from
the power management perspective since latest designs consist of
multiple power domains with individual power constraints. To
avoid any test failures, it must be avoided that the total power
consumption of the concurrently activated instruments exceeds the domain’s power limit. Particularly when considering highly
complex IEEE 1687 networks, which reveal the full potential of the standard by introducing hierarchical and optimized networks,
the power-aware test scheduling is a non-trivial task.
This paper proposes a test scheduling scheme for complex IEEE 1687 networks, which heavily orchestrates graph-based
methods. In the end, an optimized test plan is determined, which ensures, on the one hand, a minimized overall test access time
and, on the other hand, full compliance with the given power constraints. The approach’s efficacy is demonstrated on state-of-the-
art benchmark sets involving complex networks with various
power domains.