The two scientists show how to optimise the design flow and shorten time-to-market. The advent of Virtual Prototypes (VPs) at the Electronic System Level (ESL) plays an important role in modernising the system-on-chips (SoCs) design flow. Leveraging VPs and extending their use-cases for early security validation are shown as a promising direction. As the cost of fixing any security flaws increases with the stage of development, VP-based security validation can significantly avoid costly iterations. In this paper, we propose VIP-VP, a novel VP-based dynamic information flow analysis approach at the ESL.VIP-VP enables designers to validate the information flow policies of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity). Experimental results including a real-world VP-based SoC demonstrate the scalability and applicability of the proposed approach.
With this year's award, scientists from the DFKI Cyber-Physical Systems research department receive the FDL's Best Paper Award for their outstanding research work for the second year in a row.
