Project | ExaVerse

The design of modern chip architectures is increasingly moving towards heterogeneous structures, where specialized computations are performed by optimized processor units such as specific floating-point operations or matrix calculations for AI algorithms. In the ExaVerse project, the verification of such systems based on the RISC-V architecture is being investigated. The verification platform developed in the predecessor projects VerSys and ECXL, which was previously focused on individual CPU cores, will be expanded to encompass an entire system with additional units such as AI accelerators and GPUs. The verification platform allows the system under development to be modeled as a virtual prototype, enabling the verification and development of software before the hardware is even manufactured. Furthermore, the verification process is efficiently supported by the use of large language models (LLMs). These have proven successful in translating natural language inputs into formal expressions and vice versa. This capability will be utilized to interactively support chip designers by creating automated test suites and test datasets, modifying designs, and detecting errors in the hardware description language. The LLM support will be systematically integrated into the verification protocol of an existing virtual prototype (VP) for RISC-V-based systems.