Skip to main content Skip to main navigation

Publications

Page 1 of 8.

  1. Niklas Bruns; Vladimir Herdt; Rolf Drechsler

    Processor Verification using Symbolic Execution: A RISC-V Case-Study

    In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

  2. Tim Meywerk; Vladimir Herdt; Rolf Drechsler

    Coverage-guided Fuzzing for Plan-based Robotics

    In: 15th International Conference on Agents and Artificial Intelligence (ICAART). International Conference on Agents and Artificial Intelligence (ICAART-2023), February 22-24, Lissabon, Portugal, 2023.

  3. Sören Tempel; Vladimir Herdt; Rolf Drechsler

    Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT

    In: IEEE Internet of Things Journal (IoT), Vol. o.a. IEEE, 2023.

  4. Sallar Ahmadi-Pour; Mathis Logemann; Vladimir Herdt; Rolf Drechsler

    Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

    In: Chips, Vol. 2, Pages 195-208, MDPI, 2023.

  5. Milan Funck; Sallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler

    Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification

    In: FDL. Forum on Specification & Design Languages (FDL-2023), September 12-15, Turin, Italy, IEEE, 2023.

  6. Vladimir Herdt; Daniel Große; Rolf Drechsler

    Verbessertes virtuelles Prototyping Mit RISC-V-Fallstudien

    Springer Vieweg, 2023.

  7. Pascal Pieper; Vladimir Herdt; Rolf Drechsler

    Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype

    In: Teresa Cervero; Kevin Martin; Mario Kovač; Maurizio Martina (Hrsg.). Journal of Low Power Electronics and Applications (JLPEA), Vol. 12, No. 4 (52) (Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives), MDPI, 9/2022.

  8. Sören Tempel; Vladimir Herdt; Rolf Drechsler

    Automated Detection of Spatial Memory Safety Violations for Constrained Devices

    In: 27th Asia and South Pacific Design Automation Conference (ASP-DAC). Asia and South Pacific Design Automation Conference (ASP-DAC), January 17-20, 2022.

  9. Niklas Bruns; Vladimir Herdt; Eyck Jentzsch; Rolf Drechsler

    Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

    In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2022), March 14-23, Antwerpen, Belgium, 2022.

  10. Wolfgang Ecker; Milos Krstic; Andreas Mauderer; Eyck Jentzsch; Mihaela Damian; Julian Oppermann; Andreas Koch; Peer Adelt; Wolfgang Müller; Vladimir Herdt; Rolf Drechsler; Rafael Stahl; Karsten Emrich; Daniel Müller-Gritschneder; Jan Schlamelcher; Kim Grüttner; Jörg Bormann; Wolfgang Kunz; Reinhold Heckmann; Gerhard Angst; Ralf Wimmer; Bernd Becker; Philipp Scholl; Paul Palomero Bernardo; Oliver Bringmann; Johannes Partzsch; Christian Mayr

    The Scale4Edge RISC-V Ecosystem

    In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2022), March 14-23, Antwerp, Belgium, 2022.