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Publikationen

Seite 57 von 57.

  1. Robert Wille; Rolf Drechsler; Christof Oswald; Alberto Garcia-Ortiz

    Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis

    In: Conference Proceedings Design, Automation & Test in Europe. Design, Automation & Test in Europe (DATE-12), March 12-16, Dresden, Germany, 2012.

  2. Robert Wille; Mathias Soeken; Eleonora Schönborn; Rolf Drechsler

    Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic

    In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2012. IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2012), August …

  3. Stephan Eggersglüß; Melanie Diepenbeck; Robert Wille; Rolf Drechsler

    Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints

    In: Proceedings. IEEE Workshop on RTL and High Level Testing (WRTLT-12), IEEE, 2012.

  4. Stephan Eggersglüß; Rolf Drechsler

    As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization

    In: Proceedings of the GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. GI/GMM/ITG Workshop Testmethoden und …

  5. Stephan Eggersglüß; Rolf Drechsler

    As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization

    In: Proceedings of DATE 11 - Design, Automation & Test in Europe. The European Event for Electronic System Design & Test. Design, Automation & Test in …

  6. Stephan Eggersglüß; Rolf Drechsler

    Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application

    In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 9, Pages 1411-1415, IEEE Press, 2011.