Project

VerSys

A Sound Verification Platform for Early Software Development for RISC-V based Systems

The aim of the VerSys project is to develop a consistent platform for early software development based on RISC-V technology, an instruction set architecture for microprocessors which has been developed in recent years and which is open source and free of licensing costs or royalties.

In order to take advantage of the many benefits of RISC-V, a virtual prototype will be developed into a flexible and consistent development platform. This allows the software in RISC-V-based systems to be developed parallel to the hardware, which saves development time and costs.

The application areas of VerSys can be found wherever embedded and cyber-physical systems are used, from resource-saving lightweight systems in the smart home setting to computing-intensive applications with AI support in the automotive sector.

Sponsors

Federal Ministry of Education and Research (BMBF)

Federal Ministry of Education and Research (BMBF)

Images

Publications about the project

Vladimir Herdt, Rolf Drechsler

In: 27th Asia and South Pacific Design Automation Conference (ASP-DAC). Asia and South Pacific Design Automation Conference (ASP-DAC) January 17-20 2022.

To the publication
Eyck Jentzsch, Vladimir Herdt, Rolf Drechsler

In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2022) March 14-23 Antwerpen Belgium 2022.

To the publication
Eyck Jentzsch, Vladimir Herdt, Rolf Drechsler

In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" (MBMV-2022) February 17-18 virtual 2022.

To the publication

German Research Center for Artificial Intelligence
Deutsches Forschungszentrum für Künstliche Intelligenz