Publications

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Johannes Rust; Serge Autexier; Rolf Drechsler
Design Exploration für RISC-V Prozessoren zur Optimierung von Erklärbarkeit für Maschinelles Lernen
In: 28. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2025). ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" (MBMV-2025), March 11-12, Rostock, Germany, Pages 61-65, VDE, 3/2025.
Rune Krauss; Jan Zielasko; Rolf Drechsler
FrEDDY: Modular and Efficient Framework to Engineer Decision Diagrams Yourself
In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2025), March 31 - April 2, Lyon, France, 2025.
Ruidi Qiu; Grace Li Zhang; Rolf Drechsler; Ulf Schlichtmann; Bing Li
CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design
In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2025), March 31 - April 2, Lyon, France, 2025.
Mohamed Nadeem; Chandan Kumar Jha; Rolf Drechsler
Polynomial Formal Verification of Sequential Circuits using Weighted-AIGs
In: Design, Automation and Test in Europe Conference (DATE). Design, Automation & Test in Europe (DATE-2025), March 31 - April 2, Lyon, France, 2025.
Sajjad Parvin; Chandan Kumar Jha; Frank Sill Torres; Rolf Drechsler
True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFET
In: 38th International Conference on VLSI Design. International Conference on VLSI Design (VLSID-2025), 38th, January 4-8, Bengaluru, India, 2025.
Chandan Kumar Jha; Khushboo Qayyum; Muhammad Hassan; Rolf Drechsler
FARAD: Automated Formal Verification of Approximate Restoring Array Dividers
In: 38th International Conference on VLSI Design. International Conference on VLSI Design (VLSID-2025), 38th, January 4-8, Bangalore, India, 2025.
Paul Flammarion; Sajjad Parvin; Frank Sill Torres; Rolf Drechsler
Auto-OPS: A Framework For Automated Optical Probing Simulation on GDS-II
In: Proceedings of the 7th International Workshop on Secure Hardware, Architecture, and Software (SeHAS'2025). International Workshop on Secure Hardware, Architecture, and Software (SeHAS-2025), located at HiPEAC 2025, January 21, Barcelona, Spain, 2025.
Mohamed Nadeem; Rolf Drechsler
Linear Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures
In: Journal of Multiple-Valued Logic and Soft Computing, Vol. 09, Old City Publishing, 2025.
Martha Schnieber; Rolf Drechsler
Automated polynomial formal verification using generalized binary decision diagram patterns
In: Philosophical Transactions of the Royal Society A, The Royal Society Publishing, 2025.
Mohamed Nadeem; Chandan Jha; Rolf Drechsler
Polynomial Formal Verification of Multi-Valued Approximate Circuits within Constant Cutwidth
In: IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2025.