Skip to main content Skip to main navigation

Publication

Device-to-logic variability propagation in RRAM-based logic-in-memory architectures

Ankit Bende; Simranjeet Singh; Chandan Jha; Daniele Storelli; Dennis Nielinger; Rolf Drechsler; Regina Dittmann; Stephan Menzel; Farhad Merchant; Vikas Rana
In: Neuromorphic Computing and Engineering, IOP Science, 2026.

Abstract

Logic-in-memory (LiM) has emerged as a promising paradigm to address the von Neumann bottleneck by integrating data storage and in-situ computation. Resistive random-access memory (RRAM) is a strong candidate for LiM owing to its non-volatility, fast switching characteristics, and compatibility with CMOS integration. However, intrinsic cycle-to-cycle (C2C) and device-to-device (D2D) variability fundamentally limits logic reliability in RRAM-based LiM architectures, necessitating well-defined device specifications and variability margins to ensure correct operation. In this work, we experimentally demonstrate a CMOS-integrated TaO x -based 1T1R RRAM computing fabric that supports reconfigurable LiM operations, including a functionally complete Boolean set and in-memory arithmetic primitives. Through extensive statistical measurements and variability-aware statistical modeling, we systematically evaluate the impact of key variability sources, SET voltage (V SET ), low resistance state (LRS), and high resistance state (HRS), on logic correctness and identify the dominant contributors to computational failure. Finally, we derive the device specifications and requirements to achieve error-free stateful LiM operations in the 1T1R RRAM arrays.