Publikation

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core

Sajjad Parvin; Sallar Ahmadi-Pour; Chandan Kumar Jha; Frank Sill Torres; Rolf Drechsler

In: Proceedings of the First Workshop on State-of-the-Art Nanoelectronics in the Framework of Security and Artificial Intelligence (NanoSecAI 2023). Workshop on State-of-the-Art Nanoelectronics in the Framework of Security and Artificial Intelligence (NanoSecAI-2023), located at 2023 IEEE COINS conference, July 24, Berlin, Germany, IEEE Xplore, 2023.

Zusammenfassung

Optical Probing Attacks (OPA) have been shown as an effective solution to bypass several known protection schemes of integrated circuits and to read out sensitive information, like security keys or Intellectual Property (IP). As a countermeasure, we propose a methodology for designing high-performance OPAhardened digital circuits. Several existing solutions for OPA-hardened designs require changes in the fabrication process, resulting in a higher cost. Other approaches suffer from notable performance reductions and require significant changes in the employed gate libraries. In this work, we alleviate these limitations and propose a methodology to design high-performance OPA-hardened circuits. We achieve this by using a two-step methodology. First, we design a high-performance, and Low optical Leakage Dual-Rail Logic (LoL-DRL) gate library based on a standard CMOS gate library. That means, no complete redesign of the layout is required, unlike comparable approaches. Second, we propose a lightweight synthesis technique to synthesize OPA-hardened circuits from conventional circuits. Furthermore, we applied our methodology on a RISC-V core to design the first OPA-hardened RISC-V core named Lo-RISK. Our method ensures a negligible performance penalty, however at notable costs in terms of area and power.