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Publication

LLM-based Generation of High-Level Benchmarks for MVL Designs

Rolf Drechsler
In: IEEE International Symposium on Multiple-Valued Logic. IEEE International Symposium on Multiple-Valued Logic (ISMVL-2026), May 19-21, Sendai, Japan, 2026.

Abstract

Benchmark circuits are crucial for evaluating and comparing algorithms in Electronic Design Automation (EDA). While extensive benchmark suites exist for binary logic, only a few are available for Multi-Valued Logic (MVL) circuits. Existing methods often rely on encoded binary circuits, which do not adequately capture the structural properties of MVL designs. In this work, we demonstrate that Large Language Models (LLMs) can be used to generate meaningful MVL benchmarks with minimal effort on a higher abstraction level. As a proof of concept, we present the automatic generation of an 8-bit Arithmetic Logic Unit (ALU) operating over GF(3). The resulting benchmark exhibits realistic design structures and functional diversity, illustrating the potential of LLM-based generation for future MVL synthesis and verification research.