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Publication

Approximated MAGIC-ReRAM Adder Circuits for Low-Latency In-Memory Computing

Saeideh Nabipour; Chandan Jha; Saeideh Shirinzadeh; Rolf Drechsler
In: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2026), April 27-29, Bratislava, Slovakia, 2026.

Abstract

Approximate computing improves performance and energy efficiency for error-tolerant applications such as machine learning. Prior work has proposed approximate adder libraries for memristive crossbars using IMPLY and MAGIC stateful logic, primarily focusing on area optimization or fixed crossbar mappings. However, the impact of functional approximation under fully parallel crossbar execution remains largely unexplored. This work presents a framework for generating, mapping, and evaluating approximate Ripple Carry Adders (RCAs) implemented using MAGIC logic in memristive ReRAM crossbars under fully parallel crossbar execution. We explore a large design space by generating 458,752 approximate 8-bit RCA variants. Each design is synthesized into NOR/NOT logic and mapped onto a MAGIC crossbar at the micro-operation level. The resulting implementations are evaluated in terms of latency, memristor count, and functional accuracy using Mean Squared Error (MSE) and Mean Absolute Error (MAE). Pareto-optimal designs reveal key trade-offs between latency, area, and approximation error, highlighting the potential of MAGIC-based in-memory arithmetic for low-latency and energy-efficient computing

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