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Evaluating an open-source hardware approach from HDL to GDS for a security chip design — a review of the final stage of project HEP

Tim Henkes; Steffen Reith; Marc Stöttinger; Norbert Herfurth; Goran Panic; Julian Wälde; Fabian Buschkowski; Pascal Sasdrich; Christoph Lüth; Milan Funck; Tuba Kiyan; Arnd Weber; Detlef Boeck; René Rathfelder; Torsten Grawunder
In: Design, Automation and Test in Europe. Design, Automation & Test in Europe (DATE-2024), March 25-27, Valencia, Spain, 2024.


The project ``Hardening the value chain through open-source, trustworthy EDA tools and processors (HEP)'' uses open-source, free components and tools for the production of a prototypical security chip. A design flow using only free and open tools from the abstract description in SpinalHDL via OpenROAD down to the GDS-file for tape-out has been established, and first ASICs produced at IHP. The prototypical hardware security module (HSM) produced in this way provides, among other things, a processor based on VexRiscv, a cryptographic accelerator and masking of cryptographic keys. The open development tools used in the process were integrated into a common environment and expanded to include missing functionality. Subsequently, the whole tool chain and its peripherals are wrapped into a new Nyx container. The easy accessibility of the used process significantly reduces the learning curve for chip design. Additionally, we provide tools for formal verification and masking against side-channel attacks in our design flow. Interest in the results of project HEP has been shown in publications in which industrial partners participated, such as Elektrobit, Hensoldt Cyber, IAV, Secure-IC and Swissbit Germany.