Publikation
Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs
Sallar Ahmadi-Pour; Luca Müller; Rolf Drechsler
In: Forum on specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL-2026), September 9-11, Rom, Italy, 2026.
Zusammenfassung
With the growing complexity of modern Integrated
Circuits (ICs), cross-level verification increasingly relies on multiple coverage metrics to assess verification progress and quality.
While Virtual Prototypes (VPs) enable efficient verification across
abstraction layers, the impact of verification parameters on
bug-finding effectiveness remains poorly understood. This work
presents an exploratory analysis of verification parameters in a
Constrained Random Verification (CRV)-based cross-level setup.
Using a RISC-V Register-Transfer Level (RTL) implementation
and a binary-compatible VP, we systematically explore a parameterized CRV-based verification flow, varying instruction sequence
length, mutation location, and mutation count, and assess their
impact using mutation, functional, and code coverage metrics.
Our results show that different coverage metrics exhibit distinct
saturation behaviors as verification parameters are varied. In
particular, mutation coverage continues to reveal bug-finding
effectiveness in scenarios where functional and code coverage
stabilize, highlighting the importance of cross-checking trends
across multiple metrics rather than maximizing individual coverage values in isolation.