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Publikationen

Zeige Ergebnisse 951 bis 960 von 15033.
  1. Preserving and Improving Verifiability of Circuits Based on Local Transformations

    In: 26th IEEE Latin American Test Symposium 2025. IEEE Latin American Test Symposium (LATS-2025), March 11-14, San Andres, Colombia, 2025.

  2. Sabine Janzen; Hannah Stein; Katharina Trinley; Cicy Kuriakose Agnes; Vaibhav Jain; Karan Rajeshkar; Nirav Shenoy; Anika Rusch; Sujatro Ghosh; Wolfgang Maaß

    ESCADE: Energy-efficient Artificial Intelligence for Cost-effective and Sustainable Data Centers

    In: RPEatCAiSE25: Research Projects Exhibition at the International Conference on Advanced Information Systems Engineering, June 16-20, 2025, Vienna, Austria. International Conference on Advanced Information Systems Engineering (CAiSE-2025), 6/2025.

  3. Jan Kleinekathöfer; Alireza Mahzoon; Rolf Drechsler

    Lower bound proof for the size of BDDs representing a shifted addition

    In: Information Processing Letters, Vol. 24, Pages 140-151, IEEE, 2025.

  4. Bernhard J. Berger; Christina Plump; Rolf Drechsler

    Why less is sometimes more: Using Boolean literals to solve 2048

    In: IT - information technology (IT), Vol. 66, Pages 4-5, De Gruyter Brill, 2025.

  5. Lennart Weingarten; Kamalika Datta; Sallar Ahmadi-Pour; Abhoy Kole; Rolf Drechsler

    Ensuring Correctness Efficiently for RISC-V Processors with Customised Multiplier Designs

    In: Design and Verification of Cyber-Physical Systems: From Theory to Applications, Science Direct, 2025.

  6. Towards Proofs for SCA-based Efficient Formal Verification of Complex Arithmetic Circuits

    In: 2025 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS). International Conference on Design, Test and Technology of Integrated Systems (DTTIS-2025), 20th, October 15-17, Athens, Greece, IEEE Xplore, 2025.

  7. Lennart Weingarten; Kamalika Datta; Abhoy Kole; Maya Ambalapat; Saeideh Nabipour; Indranil Sen Gupta; Rolf Drechsler

    A Complete Synthesis and Verification Approach for MAGIC Based In-Memory Computing

    In: 2025 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS). International Conference on Design, Test and Technology of Integrated Systems (DTTIS-2025), 20th, October 15-17, Athens, Greece, IEEE Xplore, 2025.

  8. Lennart Weingarten; Kamalika Datta; Rolf Drechsler

    ForMAt: Formal Verification of Scalable Multiply and Accumulate Units

    In: Forum on specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL), September 10-12, St. Goar, Germany, 2025.

  9. BDD Meets SAT: Binary Hybrid Diagrams for Efficient Generation of Multiple Solutions

    In: Forum on specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL-2025), September 10-12, St. Goar, Germany, 2025.

  10. Deepak Ravibabu; Sallar Ahmadi-Pour; Muhammad Hassan; Abhoy Kole; Chandan Jha; Rolf Drechsler

    System-Level Design Space Exploration for Matrix Multiplication using Compute-In-Memory Unit

    In: Forum on specification & Design Languages (FDL). Forum on Specification & Design Languages (FDL), September 10-12, Schloss Rheinfels, Germany, 2025.