Skip to main content Skip to main navigation

Publications

Displaying results 1831 to 1840 of 15005.
  1. Designing Memory Protection for a RISC-V Nano-VP

    In: Proceedings of the 3rd Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec'25). Workshop on Nano Security: From Nano-Electronics to Secure Systems (NanoSec-25), March 29 - April 2, Lyon, France, 2025.

  2. Optimizing Hardware for Neural Network Inference using Virtual Prototypes

    In: RISC-V Summit Europe. RISC-V Summit Europe, May 12-15, Paris, France, 2025.

  3. Kemal Çağlar Coşkun; Chandan Jha; Muhammad Hassan; Rolf Drechsler

    Formal Verification of Error Bounds for Resistive-Switching-based Multilevel Matrix-Vector Multipliers

    In: 26th International Symposium on Quality Electronic Design (ISQED'25). International Symposium on Quality Electronic Design (ISQED-2025), April 23-25, San Francisco, USA, 2025.

  4. Till Schnittka; Chandan Jha; Sallar Ahmadi-Pour; Rolf Drechsler

    RIVER: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars

    In: 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2025), May 5-7, Lyon, France, 2025.

  5. Karl Aaron Rudkowski; Sallar Ahmadi-Pour; Rolf Drechsler

    CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution

    In: 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), May 5-7, 2025.

  6. LLM-assisted Performance Estimation of Embedded Software on RISC-V Processors

    In: 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2025), May 5-7, Lyon, France, 2025.

  7. Multi-Input MAGIC Synthesis and Verification for In-Memory Computing Design

    In: IEEE International Symposium on Multiple-Valued Logic (ISMVL). IEEE International Symposium on Multiple-Valued Logic (ISMVL-2025), June 5-6, Montreal, Canada, 2025.

  8. Daniel Stattkus; Lorena Göritz; Laura Hein; Jannick Eckle; Maja-Gwendoline Reibold; Sascha Schuhmacher; Julia Knopf; Oliver Thomas

    YouCodeGirls – Nutzung von Künstlicher Intelligenz zur zielgruppengerechten Unterstützung von Lernprozessen

    In: HMD - Praxis der Wirtschaftsinformatik (HMD), Vol. 0, Pages 1-21, Springer, 2/2025.

  9. CABSL 2 – Specification Language for Complex Behaviors

    In: Ana Patrícia Fontes Magalhães Mascarenhas; Alexander Antoine Ferrein; Rudi Villing (Hrsg.). RoboCup 2025: Robot World Cup XXVIII. RoboCup International Symposium (RoboCup-2025), July 21, Salvador, Brazil, Lecture Notes in Artificial Intelligence (LNAI), Vol. 16460, Springer, 2026.