Publikationen

In: IEEE Transactions on Circuits and Systems II: Express Briefs, IEEE, 2023.

In: 35. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ). GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ-2023), February 26-28, Erfurt, Germany, 2023.

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In: International Symposium on Quality Electronic Design (ISQED'23). International Symposium on Quality Electronic Design (ISQED-2023), April 5-7, San Francisco, USA, 2023.

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In: International Symposium on Quality Electronic Design (ISQED'23). International Symposium on Quality Electronic Design (ISQED-2023), April 5-7, San Francisco, USA, 2023.

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In: IEEE Internet of Things Journal (IoT), Vol. o.a. IEEE, 2023.

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In: Design, Automation and Test in Europe Conference (DATE 2023). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

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In: 28th Asia and South Pacific Design Automation Conference (ASP-DAC). Asia and South Pacific Design Automation Conference (ASP-DAC-2023), January 16-19, Tokyo, Japan, 2023.

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In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

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In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

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In: Design, Automation and Test in Europe (DATE). Design, Automation & Test in Europe (DATE-2023), April 17-19, Antwerp, Belgium, 2023.

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Publikationen

Aktive Filter:

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Polynomial Formal Verification of a Processor: A RISC-V Case Study

VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking

Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - a RISC-V Case Study

Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network

FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing

Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits

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