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Publikationen

Zeige Ergebnisse 251 bis 260 von 15033.
  1. Luca Müller; Mohamed Nadeem; Rolf Drechsler

    Cutwidth Decomposition on Circuit-AIGs: Taming Verification Complexity of Arithmetic Circuits

    In: 27th International Symposium on Quality Electronic Design. International Symposium on Quality Electronic Design (ISQED-2026), April 8-10, San Francisco, USA, 2026.

  2. LiREC-Net: A Target-Free and Learning-Based Network for LiDAR, RGB, and Event Calibration

    In: Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR). International Conference on Computer Vision and Pattern Recognition (CVPR-2026), Computer Vision and Pattern Recognition, located at IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR), June 3-7, Denver, Colorado, USA, Computer Vision Foundation (CVF) and IEEE, 2026.

  3. Martha Schnieber; Rolf Drechsler

    Path Delay Fault Testable KFDD Circuits with Polynomial Test Pattern Generation

    In: 31st IEEE European Test Symposium. IEEE European Test Symposium (ETS-2026), May 25-29, Chania, Greece, IEEE, 2026.

  4. Jing Yang; Nils Feldhus; Salar Mohtaj; Leonhard Hennig; Qianli Wang; Eleni Metheniti; Sherzod Hakimov; Charlott Frederike Jakob; Veronika Solopova; Konrad Rieck; David Schlangen; Sebastian Möller; Vera Schmitt

    Order in the Evaluation Court: A Critical Analysis of NLG Evaluation Trends

    1/2026.

  5. Hans-Georg Fill; Jennifer Horkoff; Peter Fettke; Julius Köppke

    Generative AI and Conceptual Modeling

    In: Oliver Hinz (Hrsg.). Business & Information Systems Engineering (BISE), Vol. 68, Pages 1-5, Springer Nature LINK, Wiesbaden, 2/2026.

  6. Measurement-Driven Adaptive Low-Overhead Implementation of Multi-Controlled Toffoli Gates

    In: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2026), April 27-29, Bratislava, Slovakia, 2026.

  7. Approximated MAGIC-ReRAM Adder Circuits for Low-Latency In-Memory Computing

    In: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2026), April 27-29, Bratislava, Slovakia, 2026.

  8. Fan-In Aware Graph-Based Optimization for MAC-Based In-Memory Computing

    In: Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS-2026), April 27-29, Bratislava, Slovakia, 2026.